EC8552 COMPUTER QUIZ – IV UNIT MEMORY & I/O ORGANIZATION CAO ONLINE QUIZ

EC8552 COMPUTER QUIZ – IV UNIT MEMORY & I/O ORGANIZATION CAO ONLINE QUIZ

Welcome to your COMPUTER QUIZ – EC8552 IV UNIT MEMORY & I/O ORGANIZATION CAO ONLINE QUIZ

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What is the high speed memory between the main memory and the CPU called?
Whenever the data is found in the cache memory it is called as?
When the data at a location in cache is different from the data located in the main memory, the cache is called?
Which of the following is not a write policy to avoid Cache Coherence?
Which of the following is an efficient method of cache updating?
In ____________ mapping, the data can be mapped anywhere in the Cache Memory?
The transfer between CPU and Cache is?
The reason for the implementation of the cache memory is ?
The effectiveness of the cache memory is based on the property of ?
The temporal aspect of the locality of reference means?
The spatial aspect of the locality of reference means?
The correspondence between the main memory blocks and those in the cache is given by ?
The algorithm to remove and place new contents into the cache is called?
The write-through procedure is used?
The bit used to signify that the cache location is updated is?
The copy-back protocol is used?
The approach where the memory contents are transferred directly to the processor from the memory is called?
Memory unit accessed by content is called?
The performance of cache memory is frequently measured in terms of a quantity called?
The cache memory of 1K words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?
A page fault?
If a block can be placed at every location in the cache, this cache is said to be?
The information when is written in the cache, both to the block in the cache and the block present in the lower-level memory, refers to?
Average access time of memory for having memory-hierarchy performance is given as?
As segment or a page is normally used for block, page-fault and the address-fault is used for?
The block frame address are divided into the?
The victim buffer's performance and the operation is almost similar to?
The virtual memory producing the virtual-addresses, are translated by?
Per memory reference, the miss-rate can be turned into the per instruction misses rate by?
Address translation cache is referred to as a?
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