EC8552 MCQ TEST – COMPUTER ARCHITECTURE EC8552 IMPORTANT MODEL TEST October 31, 2020 admin Leave a comment Welcome to your EC8552 MCQ TEST - COMPUTER ARCHITECTURE EC8552 IMPORTANT MODEL TEST Your Name Your Email The amount of ROM needed to implement a 4 bit multiplier is?64 bits128 bits1 Kbits2 Kbits Register renaming is done in pipelined processors?as an alternative to register allocation at compile timefor efficient access to function parameters and local variablesto handle certain kinds of hazardsas part of address translation Consider the data given in previous question. The size of the cache tag directory is ?160 Kbits136 bits40 Kbits32 bits Consider the data from above question. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?222 nanoseconds888 nanoseconds902 nanoseconds968 nanoseconds Which of the following are NOT true in a pipelined processor?Bypassing can handle all RAW hazardsRegister renaming can eliminate all register carried WAR hazardsControl hazard penalties can be eliminated by dynamic branch prediction The use of multiple register windows with overlap causes a reduction in the number of memory accesses for?Function locals and parametersRegister saves and restoresInstruction fetches In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is?before effective address calculation has startedduring effective address calculationafter effective address calculation has completedafter data cache lookup has completed The cache hit ratio for this initialization loop is?0%25%50%75% Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?Neither vectored interrupt nor multiple interrupting devices are possibleVectored interrupts are not possible but multiple interrupting devices are possibleVectored interrupts and multiple interrupting devices are both possibleVectored interrupt is possible but multiple interrupting devices are not possible The performance of a pipelined processor suffers if?the pipeline stages have different delaysconsecutive instructions are dependent on each otherthe pipeline stages share hardware resourcesall of the above More than one word are put in one cache block to?exploit the temporal locality of reference in a programexploit the spatial locality of reference in a programreduce the miss penaltynone of the above Where does the swap space reside?RAMDiskROMOn-chip cache Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?Transparent DMA and Polling interruptsCycle-stealing and Vectored interruptsBlock transfer and Vectored interruptsBlock transfer and Polling interrupts Which of the following statements about relative addressing mode is FALSE?It enables reduced instruction sizeIt allows indexing of array elements with same instructionIt enables easy relocation of dataIt enables faster address calculations than absolute addressing Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relative addressing Which of the following is true?Unless enabled, a CPU will not be able to process interruptsLoop instructions cannot be interrupted till they completeA processor checks for interrupts before executing a new instructionOnly level triggered interrupts are possible in microprocessors Relative mode of addressing is most relevant to writing?co-routinesposition-independent codeshareable codeinterrupt handerls For the daisy chain scheme of connecting I/O devices, which of the following statement is true?It gives non-uniform priority to various devicesIt gives uniform priority to all devicesIt is only useful for connecting slow devices to a processorIt requires a separate interrupt pin on the processor for each device Which of the following addressing mode is best suited to access elements of an array of contiguous memory locations ?Indexed addressing modeBase Register addressing modeRelative address modeDisplacement mode Relative mode of addressing is most relevant to writing?Flooding gunCollectorPosition – independent codeInterrupt Handlers The minimum time delay between the initiation of two independent memory operations is called?Access timeCycle timeRotational timeLatency time The register that stores the bits required to mask the interrupts is ______?Status registerInterrupt service registerInterrupt mask registerInterrupt request register In ______ addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction?Register directRegister indirectBase indexedDisplacement The _____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction?Base indexedBase indexed plus displacementIndexedDisplacement In _____ method, the word is written to the block in both the cache and main memory, in parallel?Write throughWrite backWrite protectedDirect mapping A CPU handles interrupt by executing interrupt service subroutine __________?by checking interrupt register after execution of each instructionby checking interrupt register at the end of the fetch cyclewhenever an interrupt is registeredby checking interrupt register at regular time interval The device which is used to connect a peripheral to bus is known as?control registerinterfacecommunication protocolnone of these The Memory Address Register?is a hardware memory device which denotes the location of the current instruction being executedis a group of electrical circuit, that performs the intent of instructions fetched from memorycontains the address of the memory location that is to be read from or stored intocontains a copy of the designated memory location specified by the MAR after a "read" or the new contents of the memory prior to a "write" More than one word are put in one cache block to?exploit the temporal locality of reference in a programexploit the spatial locality of reference in a programreduce the miss penaltynone of these In comparison with static RAM memory, the dynamic Ram memory has?lower bit density and higher power consumptionhigher bit density and higher power consumptionlower bit density and lower power consumptionhigher bit density and lower power consumption In the Big-Endian system, the computer stores?MSB of data in the lowest memory address of data unitLSB of data in the lowest memory address of data unitMSB of data in the highest memory address of data unitLSB of data in the highest memory address of data unit Temporal cohesion means?Coincidental cohesionCohesion between temporary variablesCohesion between local variablesCohesion with respect to time Various storage devices used by an operating system can be arranged as follows in increasing order of accessing speed?Magnetic tapes → magnetic disks → optical disks → electronic disks → main memory → cache → registersMagnetic tapes → magnetic disks → electronic disks → optical disks → main memory → cache → registersMagnetic tapes → electronic disks → magnetic disks → optical disks → main memory → cache → registersMagnetic tapes → optical disks → magnetic disks → electronic disks → main memory → cache → registers Of the following, which best characterizes computers that use memory-mapped I/O?The computer provides special instructions for manipulating I/O portsI/O ports are placed at addresses on the bus and are accessed just like other memory locationsTo perform I/O operations, it is sufficient to place the data in an address register and call channel to perform the operationI/O can be performed only when memory management hardware is turned on Which of the following mapping is not used for mapping process in cache memory?Associative mappingDirect mappingSet-Associative mappingSegmented - page mapping Suppose a processor does not have any stack pointer register. Which of the following statements is true?It cannot have subroutine call instructionIt can have subroutine call instruction, but no nested subroutine callsNested subroutine calls are possible, but interrupts are notAll sequences of subroutine calls and also interrupts are possible A processor needs software interrupt to?test the interrupt system of the processorimplement co-routinesobtain system services which need execution of privileged instructionsreturn from subroutine A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged?a hardware interrupt is neededa software interrupt is neededa privileged instruction (which does not generate an interrupt) is neededa non-privileged instruction (which does not generate an interrupt is needed In 2' s complement addition, overflow?is flagged whenever there is carry from sign bit additioncannot occur when a positive value is added to a negative valueis flagged when the carries from sign bit and previous bit matchnone of the above In the absolute addressing mode?the operand is inside the instructionthe address of the operand is inside the instructionthe register containing address of the operand is specified inside the instructionthe location of the operand is implicit The performance of a pipelined processor suffers if?the pipeline stages have different delaysconsecutive instructions are dependent on each otherthe pipeline stages share hardware resourcesall of the above Which of the following addressing modes are suitable for program relocation at run time?Absolute addressing & Indirect addressingAbsolute addressing & Based addressingBased addressing & Relative addressing More than one word is put in one cache block to?Exploit temporal locality references in a programExploit spatial locality references in a programReduce miss penaltyAll of these Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?I and II onlyII and III onlyI and III onlyI, II and III SIMD represents an organization that ?refers to a computer system capable of processing several programs at the same timerepresents organization of single computer containing a control unit, processor unit and a memory unitincludes many processing units under the supervision of a common control unitnone of the above Floating point representation is used to store?Boolean valueswhole numbersreal integersintegers In computers, subtraction is generally carried out by?9’s complement10’s complement1’s complement2’s complement The average time required to reach a storage location in memory and obtain its contents is called the?seek timeturnaround timeaccess timetransfer time The idea of cache memory is based?on the property of locality of referenceon the heuristic 90-10 ruleon the fact that references generally tend to clusterall of the above Which of the following is lowest in memory hierarchy?Cache memorySecondary memoryRegistersRAM The circuit used to store one bit of data is known as?EncoderOR gateFlip FlopDecoder Time is Up!